GMV is expanding its GNSS-User Segment Navigation team in Castilla-La Mancha, Spain. You will help migrate architecture from Xilinx MPSoC/FPGA to an ASIC solution and contribute to RTL development, verification and ASIC flow with a strong emphasis on accuracy and innovation. Idóneo candidates have a background in digital hardware design and experience with SystemVerilog, UVM and related tools, plus embedded ARM/RISC-V processors and HW/SW partitioning.
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📌 ASIC Design Engineer - RTL/Verilog, Hybrid & Relocation (Madrid)
🏢 GMV
📍 Madrid