Are you looking for an innovative and consolidated place for your professional development? GMV is an experienced technology group and…

We are expanding our teams in the

GNSS-User Segment Navigation

unit to take on

projects

related to

receivers technology . We’ll get to the point; we'll tell you what's not on the web. If you want to know more about us go to GMV website.

What challenge will you be taking on? As part of the

GMV Receivers team , you will have a key role in projects related to receiver technology, contributing to the development of projects and products with strong involvement in R&D; activities. You will participate in migrating an architecture currently implemented on Xilinx MPSoC / FPGA to an ASIC solution. Additionally, you will have the opportunity to work on the analysis of the existing design, identification of reusable blocks, adaptation of the hardware architecture, and definition of the ASIC implementation flow.

Define and evolve the target architecture for ASIC.

Develop and adapt RTL blocks (VHDL/Verilog/SystemVerilog).

Analyze and optimize internal interfaces (buses, memories, synchronization, clocks, and resets).

Participate in functional verification, simulation, and design debugging.

Contribute to the ASIC flow: synthesis, timing analysis, CDC/RDC, DFT, and design closure. Document architecture, technical decisions, and validation results.

What do we need in our team? For this role, we are looking for graduates in

Electronic Engineering, Telecommunications, Computer Science, or similar , with a specialization in the field of





digital hardware programming .

Additionally, we are seeking profiles with knowledge of

digital RTL design ,

FPGA, SoC or MPSoC architectures , internal

buses ,

IP integration , and functional verification; as well as previous experience in

ASIC flow

and handling

simulation and synthesis tools .

We will also value previous knowledge of STA, DFT, scan, low-power, UPF, floorplanning or backend; verification with SystemVerilog, UVM, assertions or cocotb; embedded ARM/RISC-V processors and hardware/software partitioning; and experience with Synopsys, Cadence, Siemens EDA, Vivado, or Vitis tools.

What do we offer?

Hybrid working model and 8 weeks per year of teleworking outside your usual geographical area.

Flexible start and finish times, and intensive working hours Fridays and in summer.

Personalized career plan development, training and language learning support.

National and international mobility. Do you come from another country? We can offer you a relocation package.

Competitive compensation with ongoing reviews, adaptable compensation and discount on brands.

Wellbeing program: health, dental and accident insurance, free fruit and coffee, physical, mental and financial health training, and much more!

We promote equal opportunities in recruitment, and we are committed to inclusion and diversity.

What are you waiting for? Join us If you have any questions please do not hesitate to contact

Carolina Barber Caso , in charge of this vacancy.

Carolina Barber Caso

#J-18808-Ljbffr

📌 ASIC Design Engineer (Madrid)
🏢 GMV
📍 Madrid