03 sep
|
GMV
|
Guadalajara
GMV is expanding its GNSS-User Segment Navigation team in Castilla-La Mancha, Spain.
Revise detenidamente toda la documentación de la solicitud antes de hacer clic en el botón de solicitar al final de esta descripción.
You will help migrate architecture from Xilinx MPSoC/FPGA to an ASIC solution and contribute to RTL development, verification and ASIC flow with a strong emphasis on accuracy and innovation.
Adecuado candidates have a background in digital hardware design and experience with SystemVerilog, UVM and related tools, plus embedded ARM/RISC-V processors and HW/SW partitioning. xcskxlj
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Hay opciones de teletrabajo/trabajo desde casa disponibles para este puesto.
📌 ASIC Design Engineer - RTL/Verilog, Hybrid & Relocation (Guadalajara)
🏢 GMV
📍 Guadalajara