Job Description

Our partner is expanding their hardware verification team and is looking for a Senior Formal Verification Engineer to support advanced high performance processor development.

In this role, you will own the formal verification environment for complex vector execution blocks, working closely with microarchitecture, RTL and simulation verification teams.

You will play a key role in ensuring architectural correctness by building scalable formal testbenches, writing mathematical properties, proving datapath behavior and finding deep corner case bugs in high complexity arithmetic and execution logic.

Location: Barcelona, Spain - Hybrid

Responsibilities:

As a Senior Formal Verification Engineer, your broad responsibilities will include but are not limited to:

• Own formal verification environments for complex vector unit sub blocks
• Build scalable formal testbenches for execution pipelines and register interfaces
• Write and maintain SystemVerilog Assertions, SVA
• Verify integer and floating point arithmetic datapaths
• Apply word level modeling, bit blasting and algebraic techniques
• Drive proof convergence and resolve state space issues
• Debug counter examples and translate them into actionable RTL bugs
• Prove compliance with vector architecture specifications
• Work closely with microarchitecture and simulation verification teams
• Define the boundary between simulation and formal verification
• Review and improve assertions written by design and verification peers
• Support formal friendly RTL design practices
• Contribute to verification planning and formal sign off

Requirements:

• 5 plus years of hardware verification experience




• Strong formal verification experience in CPU, GPU, DSP or execution pipelines
• Strong arithmetic or datapath formal verification knowledge
• Strong SystemVerilog and SVA
• Experience with JasperGold, VC Formal, OneSpin or similar tools
• Experience with proof convergence, abstraction and black boxing
• Vector, floating point or integer execution unit experience
• Python, Tcl or Bash scripting
• Bachelor, Master or PhD in a relevant technical field
• English level C1

Preferred / Valued knowledge:

• RISC V experience is highly valued
• Vector, floating point or out of order execution knowledge is valued
• Emulation experience with Veloce or ZeBu is valued
• AXI, CHI or bus interface knowledge is valued
• CPU, GPU, DSP, NPU, AI accelerator or high performance SoC experience is valued

What’s in it for you?

Our client offers an exciting, challenging role in a collaborative, dynamic environment.

The right person will find many career growth opportunities in their company, whether you want to advance your technical skills or aspire to leadership in the future.

Benefits:

- Adaptable working hours
(office open between 7 AM and 9 PM, employees manage their own schedule)

- Hybrid working model

- One week per year work from anywhere

- 25 days annual leave plus December 24 and 31

- €150 per month food allowance

- Private medical insurance

- One time relocation bonus paid with the first salary

- Support with housing search through an agency

- Visa support if required

- Relocation support for family

- Virtual shares

- Language classes
(Spanish, English, Catalan)

- Tax incentive

Required Skill Profession

Computer Occupations

📌 Senior Formal Verification Engineer Vector Unit (VU) (Barcelona)
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