Job Reference

294_26_CS_CORE_RE2

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Job title

Research Engineer - RTL OoO Core Development - DARE (RE2)

Closing Date

Wednesday, 19 August, ****

About BSC

The Barcelona Supercomputing Center - Centro Nacional de Supercomputación (BSC-CNS) is the leading supercomputing center in Spain. It houses MareNostrum, one of the most powerful supercomputers in Europe, was a founding and hosting member of the former European HPC infrastructure PRACE (Partnership for Advanced Computing in Europe), and is now hosting entity for EuroHPC JU, the Joint Undertaking that leads large-scale investments and HPC provision in Europe. The mission of BSC is to research, develop and manage information technologies in order to facilitate scientific progress. BSC combines HPC service provision and R&D; into both computer and computational science (life, earth and engineering sciences) under one roof, and currently has over **** staff from 60 countries.

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We are particularly interested for this role in the strengths and lived experiences of women and underrepresented groups to help us avoid perpetuating biases and oversights in science and IT research. In instances of equal merit, the incorporation of the under-represented sex will be favoured.

We promote Equity, Diversity and Inclusion, fostering an environment where each and every one of us is appreciated for who we are, regardless of our differences.

If you consider that you do not meet all the requirements, we encourage you to continue applying for the job offer. We value diversity of experiences and skills, and you could bring unique perspectives to our team.

Context and Mission

DARE European Supercomputing Project

DARE Objectives

- Contribute to European technological sovereignty by building a complete software/hardware ecosystem for HPC based on RISC-V, optimized for critical EU HPC applications by using a co-design approach.
- Produce a long-term roadmap with a critical timeline, milestones, and all the necessary activities needed to build and deploy post-exascale systems in Europe using European technology.
- Deliver EU-owned, energy-efficient, high-end processors and accelerators designed for industrial-grade HPC and Cloud solutions.

Key Duties




- Research of computer architectural techniques and development of RTL hardware structures related to superscalar OoO core design to improve the efficiency, scalability, and performance of a current RISC-V core.
- Review and analyze the state-of-the-art performance techniques for OoO processor architectures to identify the most effective approaches.
- Design RTL structures by implementing the selected techniques for RISC-V CPU architectures. Implement complex control logic, data paths, and microarchitectural features in SystemVerilog.
- Integration into RISC-V Core: This integration should provide an efficient and configurable means of RISC-V processor cores with the new capabilities, demonstrating a tradeoff balance with performance improvements.
- Verification and Validation: Develop a verification strategy with CoCoTB for the derived modules and Python hardware modeling. Implement verification tests and validation procedures to ensure correctness and functionality.
- Performance Evaluation: Evaluate the impact of the new capabilities on the RISC-V processor core through extensive simulation and benchmarking. Measure the improvements in terms of execution efficiency, reduced cycle count, and overall performance.
- Follow the methodology and quality standards for the code base development.
- Documentation and Reporting: Document design specifications, microarchitecture, and test plans. Prepare reports and presentations on design progress, issues, and performance metrics.
- Tool and Methodology Development: Develop and maintain scripts and tools to automate design and verification tasks. Contribute to the improvement of design and verification methodologies within the team.
- Code Quality and Maintenance: Ensure high-quality, maintainable, and reusable RTL code. Perform code reviews and provide constructive feedback to peers.
- Compliance and Standards: Ensure design compliance with industry standards and best practices. Follow project-specific guidelines and contribute to the establishment of new standards within the team.

Requirements
- Education: BS or MS in Telecommunication, Electronics, Computer Science, or Computer Engineering.
- Essential Knowledge and Professional Experience: Logic Circuit Design Knowledge.




- Essential Knowledge and Professional Experience: Proficiency in SystemVerilog.
- Essential Knowledge and Professional Experience: Computer architecture Knowledge.
- Essential Knowledge and Professional Experience: Familiarity with RISC-V Specification
- Essential Knowledge and Professional Experience: Git version control system Knowledge.
- Essential Knowledge and Professional Experience: Python and CoCoTB.
- Essential Knowledge and Professional Experience: Proficiency with standard open-source and industry tools for RTL simulation. Computer architecture Knowledge.
- Essential Knowledge and Professional Experience: Direct Programming Interface for HW Modeling and Host Interfacing. xqbhyrx
- Essential Knowledge and Professional Experience: Make, Bash, Docker
- Additional Knowledge and Professional Experience: Knowledge and experience of programming (with C, C++)
- Additional Knowledge and Professional Experience: Experience working with Linux operating system
- Competences: Good English Communication skills (written and speaking)
- Competences: Teamwork and Collaboration
- Competences: Assertive Comunication
- Competences: Adaptability
- Competences: Problem-Solving
- Competences: Critical Thinking
- Competences: Time Management
- Competences: Interpersonal Skills
- Competences: Attention to Detail

Conditions
- The position will be located at BSC within the Computer Sciences Department
- We offer a full-time contract (35h/week), a good working environment, a highly stimulating environment with state-of-the-art infrastructure, versátil working hours, extensive training plan, restaurant tickets, private health insurance, support to the relocation procedures
- Duration: Open-ended contract due to technical and scientific activities linked to the project and budget duration
- Holidays: 22 days of holidays + 6 personal days + 24th and 31st of December per our collective agreement
- Salary: we offer a competitive salary commensurate with the qualifications and experience of the candidate and according to the cost of living in Barcelona
- Starting date: Month 18

BSC-CNS is an equal opportunity employer committed to diversity and inclusion. We are pleased to consider all qualified applicants for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability or any other basis protected by applicable state or local law.

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📌 Research Engineer - Rtl Ooo Core Development - Dare (Barcelona)
🏢 Barcelona Supercomputing Center
📍 Barcelona