Barcelona Supercomputing Center seeks a Research Engineer to advance RTL OoO core development within the DARE project. You will design and verify RISC-V processor techniques and integrate new capabilities into a scalable core.The role requires strong SystemVerilog, Computer Architecture knowledge, and experience with Linux, Git, and Python-based verification. You will collaborate across teams, document results, and contribute to state-of-the-art HPC infrastructure.
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📌 Research Engineer - RTL OoO Core (RISC-V) | Flexible Hours (Barcelona)
🏢 Barcelona Supercomputing Center
📍 Barcelona
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