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in Barcelona is seeking a Functional Verification Engineer to interface with architecture, design, hardware and software teams to ensure top-level system performance.
You will develop verification environments in SystemVerilog/UVM, SystemC/C++, and run verification plans, regressions and debugging; contribute to coverage and methodology improvements.
The role is based in Barcelona with hybrid work options. xcskxlj
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Hay opciones de teletrabajo/trabajo desde casa disponibles para este puesto.