Research Engineer - RTL OoO Core Development - DARE (RE2)
The Barcelona Supercomputing Center - Centro Nacional de Supercomputación (BSC-CNS) is the leading supercomputing center in Spain.
It houses MareNostrum, one of the most powerful supercomputers in Europe, was a founding and hosting member of the former European HPC infrastructure PRACE (Partnership for Advanced Computing in Europe), and is now hosting entity for EuroHPC JU, the Joint Undertaking that leads large-scale investments and HPC provision in Europe.
The mission of BSC is to research, develop and manage information technologies in order to facilitate scientific progress.
BSC combines HPC service provision and R&D; into both computer and computational science (life, earth and engineering sciences) under one roof, and currently has over **** staff from 60 countries.
BSC-CNS YouTube Channel
We are particularly interested for this role in the strengths and lived experiences of women and underrepresented groups to help us avoid perpetuating biases and oversights in science and IT research.
DARE European Supercomputing Project
BSC Has An Open Position For a Research Engineer In The Computer Sciences Department To Be a Part Of An Active Computer Architecture Research Group Working On Designing And Developing a High-end Out-of-order Processor For The HPC Digital Autonomy With RISC-V In Europe Project Or DARE.
Contribute to European technological sovereignty by building a complete software/hardware ecosystem for HPC based on RISC-V, optimized for critical EU HPC applications by using a co-design approach.
Deliver EU-owned, energy-efficient, high-end processors and accelerators designed for industrial-grade HPC and Cloud solutions.
Research of computer architectural techniques and development of RTL hardware structures related to superscalar OoO core design to improve the efficiency,



scalability, and performance of a current RISC-V core.
Review and analyze the state-of-the-art performance techniques for OoO processor architectures to identify the most effective approaches.
Implement complex control logic, data paths, and microarchitectural features in SystemVerilog.
Integration into RISC-V Core: This integration should provide an efficient and configurable means of RISC-V processor cores with the new capabilities, demonstrating a tradeoff balance with performance improvements.
Verification and Validation: Develop a verification strategy with CoCoTB for the derived modules and Python hardware modeling.
Implement verification tests and validation procedures to ensure correctness and functionality.
Performance Evaluation: Evaluate the impact of the new capabilities on the RISC-V processor core through extensive simulation and benchmarking.
Measure the improvements in terms of execution efficiency, reduced cycle count, and overall performance.
Follow the methodology and quality standards for the code base development.
Document design specifications, microarchitecture, and test plans.
Prepare reports and presentations on design progress, issues, and performance metrics.
Tool and Methodology Development: Code Quality and Maintenance: Ensure high-quality, maintainable, and reusable RTL code.
Follow project-specific guidelines and contribute to the establishment of new standards within the team.
Education:



BS or MS in Telecommunication, Electronics, Computer Science, or Computer Engineering.
Essential Knowledge and Professional Experience: Git version control system Knowledge.
Essential Knowledge and Professional Experience: Python and CoCoTB.
Essential Knowledge and Professional Experience: Make, Bash, Docker
Knowledge and experience of programming (with C, C++)
Experience working with Linux operating system
Competences: Good English Communication skills (written and speaking)
The position will be located at BSC within the Computer Sciences Department
We offer a full-time contract (35h/week), a good working environment, a highly stimulating environment with state-of-the-art infrastructure, adaptable working hours, extensive training plan, restaurant tickets, private health insurance, support to the relocation procedures
Duration: Open-ended contract due to technical and scientific activities linked to the project and budget duration
Holidays: 22 days of holidays + 6 personal days + 24th and 31st of December per our collective agreement
Development of the recruitment process
Evaluation of previous experience and/or scientific history, degree, training, and other professional information relevant to the position.
~The recruitment panel will be composed of at least three people, ensuring at least 25% representation of women.
After reviewing the content of the applications, the panel will begin the interviews, with at least one technical and one administrative interview.
We are pleased to consider all qualified applicants for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability or any other basis protected by applicable state or local law.

📌 Research Engineer - Rtl Ooo Core Development - Dare (Re2) (Barcelona)
🏢 Barcelona Supercomputing Center
📍 Barcelona