20 ago
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TechTeamz
|
Valencia
20 ago
TechTeamz
Valencia
TechTeamz in Valencia, Spain, seeks a Digital Design Verification Engineer to verify complex mixed-signal ICs and advanced SoCs, collaborating with multidisciplinary teams from concept to tape-out.
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You'll apply SystemVerilog and UVM testbenches, develop verification plans, achieve coverage goals, and run constrained-random verification xhfqzwm using Python/Perl/TCL with standard EDA tools, while communicating in English.
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📌 Soc Verification Engineer — Systemverilog & Uvm Expert (Valencia)
🏢 TechTeamz
📍 Valencia