Digital Design Verification Engineer

Location: Valencia & Spain

About the Role

We are looking for a driven Digital Design Verification Engineer to join our system and semiconductor design hub in Valencia, Spain. You will play a critical part in verifying complex mixed-signal integrated circuits and advanced system-on-chip (SoC) architectures, working closely with multidisciplinary teams from concept to tape-out.

Required Qualifications

- Experience: Hands-on professional experience in ASIC/FPGA digital design verification, specifically with complex mixed-signal or processor-based SoCs.
- Methodologies: Proven expertise in SystemVerilog and UVM-based testbench architectures .
- Techniques: Strong background in verification-plan generation, functional/code coverage closure, and constrained-random verification.
- Tools & Scripting: Proficiency in scripting languages (such as Python, Perl, or TCL) and standard EDA simulation tools.
- Soft Skills: Excellent problem-solving abilities, strong teamwork and communication skills, and proficiency in English.

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📌 Digital Design Verification Engineer (Valencia)
🏢 TechTeamz
📍 Valencia