Digital Design Verification Engineer (Freelance / Remote)Location: Remote (Based in Spain)Project Type: Freelance / ContractRequired Skills & ExperienceProven hands-on experience in ASIC/FPGA digital design verification for complex mixed-signal or processor-based SoCs.Deep expertise in SystemVerilog and UVM (Universal Verification Methodology) testbench development.Strong background in constrained-random verification and functional/code coverage closure.Proficiency in creating and executing verification plans.Hands-on experience with standard EDA simulation tools.Strong scripting skills in Python, Perl, or TCL for regression flows and automation.Excellent remote communication and collaboration skills in English.