Bull is a story. One with a century of European innovation and a working
environment where experts design powerful, sustainable, and sovereign digital
solutions, enabling states and industries to retain full control over their data
and their AI.
Bull is also thousands of engineers, researchers and passionate tech people
shaping the future of high‑performance computing, AI, and quantum technologies.
Every day, our teams push the boundaries of what is technologically possible –
from next‑generation HPC architectures to exascale supercomputers – supported by
world‑class R&D;, more than 1,600 patents, and unique end‑to‑end capabilities
spanning hardware design, software engineering, data science and quantum
research.
We are a people‑centric, innovation‑driven company, where collaboration spans
Europe, the Americas and India. We share a common vision of a responsible and
sustainable innovation that delivers concrete impact for our customers.
We are looking for an ASIC Verification Engineer to join Bull’s innovative team.
The role involves contributing to the verification of a complex ASIC using
constraint-random, coverage-driven functional verification methodologies, based
on the UVM verification standard, as part of the development of ASICs such as
network controllers, routers, and cache coherence controllers for high-end,
high-performance Bull servers, including big data and exascale systems.
Responsibilities
* Acquire knowledge of the architecture and microarchitecture of the ASIC by
studying specifications and interacting with the architecture and logical
design teams.
* Participate in defining overall verification strategies and methodologies, as
well as the required simulation environments.
* Develop, maintain, and publish verification specifications. Define test plans
in close collaboration with the logical design team.
* Develop verification environments, test cases, and coverage models using UVM
/ SystemVerilog / C++.
* Track, analyze, and debug simulation
📌 ASIC Verification Engineer (Madrid)
🏢 Atos
📍 Madrid