Job Description
Our client is expanding their RTL team and is looking for Mid / Senior RTL and Microarchitecture Engineers with strong experience in processor architecture, acceleration or compute intensive digital design.
This role is focused on design areas such as matrix multiplication, neural processing, near data processing, systolic arrays, SIMD and integer or floating point arithmetic.
You will translate architecture and microarchitecture requirements into RTL implementation, working closely with architecture, verification and physical design teams.
Location: Barcelona, Spain - Hybrid
Responsibilities:
As a RTL / Microarchitecture Engineer, Matrix / Neural Processing (Mid / Senior), your broad responsibilities will include but are not limited to:
• Design and implement RTL modules in Verilog based on architecture and microarchitecture specifications
• Contribute to processor or accelerator components related to matrix multiplication and neural processing
• Work on near data processing, systolic arrays, SIMD or arithmetic units where required
• Translate architecture concepts into efficient and scalable RTL designs
• Collaborate closely with architecture, verification and physical design teams
• Develop and use scripts to support design, automation and integration tasks
• Participate in design reviews and technical discussions
• Support debug, integration and timing related design closure needs
Requirements:
Mid RTL / Microarchitecture Engineer
• 4 to 7 years of relevant industrial experience in RTL or microarchitecture
• Strong knowledge of Verilog
• Experience translating architecture requirements into RTL
• Experience with scripting for automation and design support
• Understanding of digital design, timing and integration workflows
• English level C1
• Bachelor, Master or PhD in Computer Science, Computer Engineering or related field
Senior RTL / Microarchitecture Engineer
• 8 plus years of relevant industrial experience in RTL or microarchitecture roles
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