My client is seeking a highly skilled and experienced Senior DFT (Design for Testability) and Post-Silicon Lead to join their team. This role is pivotal in driving the implementation of DFT strategies for complex So Cs (System on Chips) and So C chiplets in package, ensuring seamless integration with test and post-silicon validation teams. You will work with cutting-edge technology and collaborate with internal teams, external IP providers, and EDA vendors to deliver high-quality, high-performance solutions for mass production. If you are passionate about innovation and thrive in a leadership role, we encourage you to apply. International applications are welcome!Responsibilities:Lead and mentor the DFT and Post-Silicon engineering teams to foster innovation and efficiencyProvide technical direction and ensure alignment with organisational goalsPromote a culture of continuous improvement and collaboration. DFT Strategy & ExecutionDefine and implement DFT architectures to enhance testability, debug capabilities, and manufacturabilityEnsure the integration of DFT features such as scan chains, BIST (Built-In Self-Test), and JTAG interfacesOptimise DFT methodologies to minimize test time, reduce costs, and improve quality and yieldTest development & implementation:Develop and execute test plans and strategies at silicon, package, and system levelsDesign automated test solutions for production and characterisationEnsure comprehensive test coverage across all product development stages,



from pre-silicon to mass productionGuarantee high yield on final solutions, addressing chiplet complexitiesCross-functional collaboration:Collaborate with design, validation, packaging, and operations teams to ensure seamless integration of testing and manufacturabilityWork closely with product management to align with customer requirements and timelinesProcess improvement & innovation:Explore and implement new DFT methodologies and manufacturing processesLead initiatives to reduce costs, improve efficiency, and enhance quality in test and productionQualifications:Bachelor’s, Master’s, or Ph D in Computer Science, Electrical Engineering, or a related fieldProven experience with multiple tape-outs of high-performance So Cs or Si Ps for mass productionStrong expertise in post-silicon test optimisation and yield analysisDemonstrated experience in defining and implementing test strategies for high-volume productionProficiency in RTL and testbench development using System Verilog and VerilogStrong scripting skills in Shell, Tcl, and Python3Hands-on experience with Tessent and SSN methods integrated with leading EDA design flows for advanced technology nodes is highly desirableIf you are ready to take on a challenging and rewarding role in a dynamic environment, we look forward to receiving your application. Join us in shaping the future of high-performance So Cs and Si Ps.For more information and to apply, please contact Resources with your CV and a time for an initial call.

📌 Dft Lead (Barcelona)
🏢 Intellectual Capital Resources
📍 Barcelona