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Job Description:
A Digital Verification Engineer Intern to validation, integration, simulation, debugging and verification of digital and mixed-signal ICs utilizing leading edge technologies with industry standard ASIC tools. Products to be designed/verified may include power management, signal management and mixed signal functions.
Task:
- Assist with the creation of Digital Verification environments with UVM and SystemVerilog.
- Write Digital and Mixed-Signal testcases and assertions/checkers.
- Analyze and debug test results, code coverage and functional coverage.
- Support on Verification IPs and standard tests, environments, checkers, etc.




- Assist with Test Plan generation based on design requirements and product datasheets of digital / mixed-signal IC’s.
- Close interaction with Senior Digital Design, Digital Verification and Analog Design Engineers to develop System Level and Behavioral Models.
- Automation and scripting.
- Gate-Level verification.

Qualifications:
- Bachelor/MS in Electrical Engineering with emphasis in Digital Design/VLSI coursework.
- Has the ability to follow instructions/tasks according to design specifications/procedures.
- Basic knowledge of ASIC development process and digital design techniques.
- Good written/verbal communication skills and strong team work/collaboration.
- Knowledge of standard DV languages (SystemVerilog, UVM) and behavioral/RTL coding.
- Executing tasks that hit project milestone.
- Knowledge/Experience with the following is a plus:
- SCAN and Other DFT Techniques.
- Knowledge of power management industry/

📌 Digital Verification Intern (Barcelona)
🏢 Monolithic Power Systems
📍 Barcelona