My client is seeking a highly skilled and experienced Senior DFT (Design for Testability) and Post-Silicon Lead to join their team. This role is pivotal in driving the implementation of DFT strategies for complex SoCs (System on Chips) and SoC chiplets in package, ensuring seamless integration with test and post-silicon validation teams. You will work with cutting-edge technology and collaborate with internal teams, external IP providers, and EDA vendors to deliver high-quality, high-performance solutions for mass production.

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If you are passionate about innovation and thrive in a leadership role, we encourage you to apply. International applications are welcome
Responsibilities:
Lead and mentor the DFT and Post-Silicon engineering teams to foster innovation and efficiency
Provide technical direction and ensure alignment with organisational goals
Promote a culture of continuous improvement and collaboration.DFT Strategy & Execution




Define and implement DFT architectures to enhance testability, debug capabilities, and manufacturability
Ensure the integration of DFT features such as scan chains, BIST (Built-In Self-Test), and JTAG interfaces
Optimise DFT methodologies to minimize test time, reduce costs, and improve quality and yield
Test development & implementation:
Develop and execute test plans and strategies at silicon, package, and system levels
Design automated test solutions for production and characterisation
Ensure comprehensive test coverage across all product development stages, from pre-silicon to mass production
Guarantee high yield on final solutions, addressing chiplet complexities
Cross-functional collaboration:
Collaborate with design, validation, packaging, and operations teams to ensure seamless integration of testing and manufacturability
Work closely with product management to align with customer requ

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