My client is seeking a highly skilled and experienced Senior DFT (Design for Testability) and Post-Silicon Lead to join their team. This role is pivotal in driving the implementation of DFT strategies for complex SoCs (System on Chips) and SoC chiplets in package, ensuring seamless integration with test and post-silicon validation teams. You will work with cutting-edge technology and collaborate with internal teams, external IP providers, and EDA vendors to deliver high-quality, high-performance solutions for mass production. If you are passionate about innovation and thrive in a leadership role, we encourage you to apply. International applications are welcomeResponsibilities:Lead and mentor the DFT and Post-Silicon engineering teams to foster innovation and efficiencyProvide technical direction and ensure alignment with organisational goalsPromote a culture of continuous improvement and collaboration.DFT Strategy & ExecutionDefine and implement DFT architectures to enhance testability, debug capabilities,



and manufacturabilityEnsure the integration of DFT features such as scan chains, BIST (Built-In Self-Test), and JTAG interfacesOptimise DFT methodologies to minimize test time, reduce costs, and improve quality and yieldTest development & implementation:Develop and execute test plans and strategies at silicon, package, and system levelsDesign automated test solutions for production and characterisationEnsure comprehensive test coverage across all product development stages, from pre-silicon to mass productionGuarantee high yield on final solutions, addressing chiplet complexitiesCross-functional collaboration:Collaborate with design, validation, packaging, and operations teams to ensure seamless integration of testing and manufacturabilityWork closely with product management to align with customer requirements and timelinesProcess improvement & innovation:Explore and implement new DFT methodologies and manufacturing processesLead initiatives to reduce costs, impr

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