:We are seeking an experienced Senior Verification Engineer with 8+ years of industry expertise i ndigital design verification. The idóneo candidate will have a strong background in SystemVerilog an dUVM, with proven experience in block-level, subsystem, and top-level verification. Knowledge o fboth formal and dynamic verification methodologies is essential
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In this role, you will work within the Verification Team to ensure the correctness a ndfunctionality of complex microprocessor architectures at the RTL level. You will develop and app lyadvanced verification methodologies, build testbenches, run simulations, and collaborate close lywith design teams to deliver high-quality, production-ready design s.
Requiremen ts:• Master’s or PhD in Computer Science, Electrical Engineering, or a related fi eld• Proficiency in SystemVerilog and
UVM• Strong scripting skills (Python, Perl, Bash, T cl)• 8+ years of relevant industry experie nce• Hands-on experience with simulation tools and regression managem ent• Familiarity with revision control tools (git, s vn)• Proven experience in block-level, subsystem, and top-level verificat ion• Background in both formal and dynamic verification methodolog ies• Excellent problem-solving skills and attention to det ail• Strong communication and teamwork abilit ies• Proficiency in English (C1 lev el)
📌 Senior Design Verification Engineer (Barcelona)
🏢 Beagle
📍 Barcelona
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