GMV Spain is expanding its GNSS‑User Segment Navigation team to migrate an architecture from Xilinx MPSoC/FPGA to an ASIC solution. The role emphasizes RTL development, IP integration, and extensive ASIC flow activities in a cutting-edge hardware environment.
We value candidates with hands-on experience in digital hardware programming, SystemVerilog-based verification, and familiarity with industry tools (Synopsys, Cadence, Vivado). Hybrid working model and relocation support offered.
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📌 Embedded RTL Engineer – ASIC/FPGA Innovation - Madrid, Comunidad de Madrid, Spain
🏢 Talent
📍 Madrid