Capgemini Engineering Madrid is seeking a Senior RTL Engineer to lead feasibility studies, define system architecture and interfaces, and drive design from architecture to tape-out. You will perform RTL coding in Verilog/SystemVerilog (or VHDL), develop microarchitecture, and collaborate with Synthesis, STA, PD, and DFT teams to meet timing, power and area goals.
You'll benefit from a collaborative culture, versátil growth opportunities, and a comprehensive benefits package in a global