Aion Silicon is actively building a pipeline of talented engineers for future opportunities, and we’d love to hear from skilled professionals who are passionate about Design for Test.
With design centers across the UK, Spain, Hyderabad, and Morocco , we offer the flexibility to base this role in any of our integral locations. Purpose of Role To lead and own chip-level Design for Test execution, driving DFT delivery from architecture definition through pattern generation and silicon bring-up. This role ensures high-quality DFT implementation, effective debug and timing closure across test modes, and provides technical leadership within the team, while acting as a key stakeholder interface to ensure predictable and successful delivery.
Lead DFT strategy definition, implementation of DFT structures, and verification to ensure chip-level testability and project success.
Define, plan, and lead large, technically complex projects, ensuring alignment with program goals.
Apply judgment in interpreting results, conducting quantitative analysis,



and driving data-informed decisions.
Maintain and promote high-quality outputs across the team, ensuring best practices and consistency.
Collaborate effectively with team members and engineering management, fostering a productive and engaged team environment.
Mentor junior engineers and provide leadership across multi-disciplinary project teams.
A degree/masters or PhD in a relevant subject
Typically 10+ years of experience in Design for Test (DFT) engineering.
Strong experience in ATPG and test coverage improvements, pattern simulation (Zdel/SDF), and diagnosing ATE failures and silicon bring-up.
Demonstrated capability to lead DFT design projects as an expert or provide industry‑leading expertise in specific DFT areas.
Strong project management skills, with the ability to evaluate issues, define solutions, and drive project delivery.
Ability to quantify risks and estimate engineering effort

📌 Graduate Engineering Project Manager (España)
🏢 Aion Silicon
📍 España