13 ago
|
Aistech Space
|
Barcelona
13 ago
Aistech Space
Barcelona
Company Description:
Aistech Space is focused on generating affordable, recurrent, high-resolution thermal imagery of the planet to provide a new perspective of Earth's changing resources. The company is based in Barcelona and aims to revolutionize remote sensing for environmental monitoring and resource management.
What you will do:
Aistech Space is seeking an expert FPGA Design Engineer to lead the development of our next-generation image acquisition and processing payloads. You will be the architect of the "digital brain" of our systems, transforming raw high-speed sensor data into actionable insights using cutting-edge VHDL logic and hardware acceleration.
This role is not just about writing code; it is about managing the entire data lifecycle—from the physical high-speed pins of the FPGA to the integration of AI engines and DMA streaming to memory. You will work at the intersection of hardware and high-level software, ensuring our systems are fast, synchronized, and reliable in demanding environments
In this role, you are expected to work as a team, functioning as an agile,
highly collaborative unit focused on short, client-driven development iterations.
You will also be responsible for following internal standards and good practices in terms of project management, documentation, and time management, adopting an agile approach in your daily work.
The key objectives to be achieved in this position are:
Understand Aistech Space mission objectives.
Xilinx RTL Development: Design and optimize modular VHDL code for Xilinx 7-Series, UltraScale+, and Versal Adaptive SoCs.
High-Speed I/O & Connectivity: Implement and debug high-speed transceivers (GTH/GTY) for protocols such as MIPI CSI-2, PCIe Gen3/4, and 10G/25G Ethernet.
Advanced Data Path: Architect low-latency data movement using AXI4-Stream, AXI SmartConnect, and Xilinx Video DMA (VDMA) or DataMover IPs.
AI Engine Integration: Deploy and optimize neural networks using the Vitis AI flow, integrating DPU (Deep Lear
📌 FPGA Designer Engineer (Barcelona)
🏢 Aistech Space
📍 Barcelona