This Full time on site position offers great opportunities for career growth.
Main function and scope: Own and execute backend implementation flows for ASIC and/or FPGA designs.
Perform logic synthesis, constraint development, optimization, and design quality checks.
Run place and route flows, including floorplanning, placement, clock tree synthesis, routing, and physical optimization.
Drive static timing analysis and timing closure across multiple modes and corners.
Analyze and resolve timing, congestion, area, power, and signal integrity issues.
Develop, review, and maintain timing constraints, including SDC/XDC files.
Support backend sign-off activities such as timing, power, DRC/LVS, CDC/RDC, and equivalence checking, depending on project scope.
Support mixed-signal integration activities, including coordination between analog and digital implementation flows.
Work with analog designers on floorplanning, pin planning, power domains, guard rings, keep-outs, substrate noise considerations, and analog/digital interface constraints.
Support the integration of analog macros,



hard IP blocks, memories, PLLs, ADCs, DACs, sensors, or other mixed-signal IP.
Collaborate with frontend RTL designers to improve implementation quality and resolve design issues.
Work with FPGA flows including synthesis, implementation, timing analysis, bitstream generation, and hardware bring-up support.
Contribute to automation scripts and flow improvements using Tcl, Python, Bash, or similar scripting languages.
Participate in design reviews and provide technical input on architecture, feasibility, performance, power, and area trade-offs.
Support requirements analysis, traceability, and verification alignment where applicable.
Required experience and candidate profile: Telecommunications engineering, electronic engineering or equivalent.
A master in micro-electronics or applicable experience in the field.
+5 years of experience in back-end ASIC/FPGA design
Technical Requirements: Training / s

📌 Backend ASIC/FPGA Engineer at ARQUIMEA (Madrid)
🏢 Arquimea
📍 Madrid