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We are seeking a highly motivated and skilled Digital IC Designer to join our engineering team. The adecuado candidate will be responsible for the design, development, simulation, and verification of complex digital integrated circuits (ICs) for various applications. This role requires hands‑on experience with the Cadence suite of Electronic Design Automation (EDA) tools to ensure designs meet performance, power, and area specifications.
Key Responsibilities
- RTL Design & Development: Develop and implement RTL (Register Transfer Level) code using VHDL/Verilog based on design specifications.
- Simulation and Verification: Perform thorough functional verification and simulation of IC designs using Cadence verification tools (e.g., Cadence NC‑Launch/Incisive, SimVision) to validate performance and functionality.
- Synthesis and Implementation:



Work on synthesis and physical design tasks, including floorplanning, placement, clock tree synthesis, and routing using Cadence physical design platforms (e.g., Cadence Genus, Cadence Innovus).
- Timing Analysis and Signoff: Conduct static timing analysis (STA) and timing closure using tools like Cadence Tempus to ensure designs meet all timing requirements.
- Physical Verification: Perform design rule checks (DRC) and layout versus schematic (LVS) verification using tools such as Cadence Pegasus or Cadence Innovus to prepare designs for fabrication (tape‑out).
- Collaboration: Collaborate with cross‑functional teams, including system architects, analog designers, and layout engineers, to ensure seamless integration and successful product development.
- Documentation: Create and maintain comprehensive design documentation, technical reports, and test plans.

Qualifications
- Bachelor's or Master's degree in Electrical E

📌 Digital IC Designer (Barcelona)
🏢 The TMRW Foundation
📍 Barcelona