Senior Analog Design Engineer (Madrid)

Senior Analog Design Engineer (Madrid)

12 ago
|
Beagle
|
Madrid

12 ago

Beagle

Madrid

Beagle Madrid
Senior Mixed-Signal IC Design EngineerLocation: Madrid, Spain

Es posible que un gran número de candidatos se presenten a este puesto, así que asegúrese de enviar su CV y su solicitud lo antes posible.
Salary: Negotiable
Duration: Permanent
An exciting opportunity to join a high‑tech R&D; team in Madrid, developing advanced analog and mixed‑signal ICs in leading‑edge CMOS technologies. This role offers the chance to work across the full design flow — from concept and system‑level definition through to silicon validation — on innovative products used in next‑generation systems.
Key Responsibilities
- Define and specify analog and mixed‑signal blocks, including ADCs, DACs, PLLs, data interfaces, and optoelectronic circuits.
- Take ownership of AMS design from schematic to full verification in sub‑nanometric CMOS processes (65nm/28nm and below).
- Establish layout guidelines, collaborate closely with layout engineers, and review their work.
- Partner with test engineers on defining and executing test plans, analyzing lab results, and correlating with simulations.




- Work alongside system‑level engineers to create behavioural models of AMS blocks for system simulations and mixed‑signal verification.
- Support the integration of analog subsystems into complex SoCs that include significant digital processing.
- Drive innovation and R&D; by exploring new architectures, contributing to future product concepts, and supporting patent activity.
- Document and present design progress and results in internal technical reviews and meetings.

Requirements
- MSc or PhD in Electronics, Electrical, or Computer Engineering (or a related field).
- 5+ years of experience in analog and mixed‑signal IC design.
- Proven experience delivering silicon‑proven designs through all development phases — from definition and design to characterization and productization.
- Hands‑on experience designing full‑custom analog IP in sub‑nanometric CMOS (65nm/28nm or below).
- Proficient with E

📌 Senior Analog Design Engineer (Madrid)
🏢 Beagle
📍 Madrid

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