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Overview
At Akuaro, we are proudly leading the recruitment process for our partner — a European deep-tech company redefining what’s possible in high-performance computing and digital infrastructure. Specialized in cutting-edge RISC-V systems and backed by major innovation initiatives, our partner is assembling a world-class engineering team in Barcelona. They are now seeking a Senior Verification Engineer with expertise in SystemVerilog and UVM to ensure their next generation of high-performance silicon meets the highest quality standards.
Contract: Permanent – Internal team of our partner
Why This Role Is Unique
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- Join the forefront of Europe’s semiconductor revolution in CPU design and verification.
- Verify cutting-edge RISC-V processors destined for high-performance computing applications.
- Use the latest advanced verification methodologies (UVM, formal verification) on complex, modern microarchitectures.
- Full-cycle ownership – contribute from block-level verification to full system validation.
- Influence design quality from day one; your work directly impacts first-silicon success.
What You’ll Be Doing
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- Develop and maintain UVM-based testbenches for complex digital designs (CPU cores, SoC blocks).
- Define and implement comprehensive verification plans, covering all features and corner cases.
- Write and run directed and constraint-random tests to validate functionality and performance.
- Implement checkers and monitors in SystemVerilog to verify correctness of microarchitectural features.
- Execute extensive simulations and regression suites; analyze waveform dumps to debug failing tests.
- Use coverage-driven verification (functional and code coverage) to measure progress and target gaps.
- Apply formal verification te
📌 Senior Verification Engineer – Drive Quality in Next‑Gen RISC‑V CPUs (Barcelona)
🏢 Akuaro
📍 Barcelona
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