We are seeking an experienced Senior Verification Engineer with 8+ years of industry expertise indigital design verification. The idóneo candidate will have a strong background in System Verilog andUVM, with proven experience in block-level, subsystem, and top-level verification. Knowledge ofboth formal and dynamic verification methodologies is essential.In this role, you will work within the Verification Team to ensure the correctness andfunctionality of complex microprocessor architectures at the RTL level. You will develop and applyadvanced verification methodologies, build testbenches, run simulations, and collaborate closelywith design teams to deliver high-quality, production-ready designs.RequirementsMaster’s or Ph D in Computer Science, Electrical Engineering, or a related fieldProficiency in System Verilog and UVM8+ years of relevant industry experienceHands-on experience with simulation tools and regression managementFamiliarity with revision control tools (git, svn)Proven experience in block-level, subsystem, and top-level verificationBackground in both formal and dynamic verification methodologiesExcellent problem-solving skills and attention to detailStrong communication and teamwork abilities

📌 Senior Design Verification Engineer (Barcelona)
🏢 Beagle
📍 Barcelona