Senior Verification Engineer – Drive Quality In Next‑gen Risc‑v Cpus (Uvm/Systemverilog) (Distrito del Ensanche)

Senior Verification Engineer – Drive Quality In Next‑gen Risc‑v Cpus (Uvm/Systemverilog) (Distrito del Ensanche)

11 ago
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Akuaro
|
Distrito del Ensanche

11 ago

Akuaro

Distrito del Ensanche

Hireroo is seeking mid to senior and lead Verification Engineers to join our client's expanding Verification organization in Barcelona. You will verify complex RTL designs, build verification environments, and contribute to verification closure for high performance processor designs.

The role focuses on processor verification, memory and PCIe/UCIe, with collaboration across architecture and RTL teams in a hybrid Barcelona setting.

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📌 Senior Verification Engineer – Drive Quality In Next‑gen Risc‑v Cpus (Uvm/Systemverilog) (Distrito del Ensanche)
🏢 Akuaro
📍 Distrito del Ensanche

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