For a integral customer in Barcelona, we are searching for a freelance (autonomo) Senior/Expert FPGA Development Engineer to design and implement FPGA functionality using SystemVerilog for their synchronization and instrumentation platforms.

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Your work will directly power some of the most demanding applications in the world today, including quantum computing, 6G, radar, and large-scale test systems. This is a hands-on FPGA development and product implementation role centered on multi-FPGA systems - not an ASIC design position.

You'll join a highly collaborative, globally distributed R&D; organization, working alongside software, hardware, and systems engineers to develop, integrate, verify, and release FPGA technology that ships inside commercial products used by engineers around the world.

Responsibilities

- Design, implement, verify, and maintain FPGA functionality using SystemVerilog.
- Perform simulation, synthesis, implementation, timing closure, and hardware validation.
- Debug complex issues across FPGA, firmware, software, and hardware domains.

Qualifications
- BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.




- Strong professional experience in FPGA design and development using SystemVerilog.
- Hands-on experience building FPGA functionality for multi-FPGA or complex FPGA-based systems.
- Proven track record with FPGA simulation, synthesis, implementation, and timing closure.
- Experience with Xilinx FPGA devices and Vivado.
- Solid grounding in digital design fundamentals - clock domain crossing (CDC), memory architectures, interfaces, and timing analysis.
- Ability to debug and integrate FPGA solutions within larger, complex system architectures.
- Comfort with modern version control (Git) workflows, including branching, code reviews, and merge management.
- Strong communication skills and a collaborative, team-first mindset.

Nice to Have
- Experience with QuestaSim, UVM, or other advanced FPGA verification methodologies.
- Familiarity with VHDL and mixed-language FPGA projects.
- Knowledge of high-speed interfaces such as PCIe, Ethernet, or JESD204.
- Background in test and measurement systems. xqbhyrx
- Scripting skills in Python, Tcl, or C++.
- Exposure to CI/CD pipelines and automated testing workflows.

SENIORITY: Senior

START DATE: September

DURATION: 6 Months

EXTENSION: Yes

CONTRACT: Freelance

LOCATION: Barcelona

HOURS PER WEEK: 40

INTERVIEW PROCESS: 1-2 stages

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📌 FPGA Engineer (SystemVerilog) (Barcelona)
🏢 Vivid Resourcing
📍 Barcelona