Senior Verification Engineer – Drive Quality In Next‑gen Risc‑v Cpus (Uvm/Systemverilog) (Les)

Senior Verification Engineer – Drive Quality In Next‑gen Risc‑v Cpus (Uvm/Systemverilog) (Les)

09 ago
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Akuaro
|
Les

09 ago

Akuaro

Les

Hireroo is seeking mid to senior and lead Verification Engineers to join our client's expanding Verification organization in Barcelona. You will verify complex RTL designs, build verification environments, and contribute to verification closure for high performance processor designs.The role focuses on processor verification, memory and PCIe/UCIe, with collaboration across architecture and RTL teams in a hybrid Barcelona setting.#J-18808-Ljbffr

📌 Senior Verification Engineer – Drive Quality In Next‑gen Risc‑v Cpus (Uvm/Systemverilog) (Les)
🏢 Akuaro
📍 Les

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