ASIC Physical Design Implementation Engineer

European Tech Recruit are working closely with a leading microelectronics company, based in Leuven, who are looking for a talented ASIC Physical Design Implementation Engineer to join their team.

This is an initial 12 month freelance contract, with planned extensions, that will require you to work onsite in Leuven 3 days per week.

In this role you will focus on full backend (P&R;) projects from netlist-in to GDSII-out flow, for top-level chips as well as block level blocks in technologies ranging from N2 to 180nm.

Responsibilities as ASIC Physical Design Implementation Engineer :

- Direct contact with customers for future projects.
- Take the lead for partitioning and split the top level SDC file into timing budget requirements/constraints of the sub-blocks.
- Work directly with the Physical Design implementation team during the entire chip design cycle to drive signoff closure for tape-out.
- Technical voice to the customer to discuss specifications.

Requirements:





- Full understanding of the complete Cadence Innovus Place&Route; flow.
- Experience in setting-up the flow for the specific library set and foundry node used.
- Experience in setting-up low power design (UPF) and debug sdc file.
- Knowledge in Floorplanning & power grid design for top-level as well as blocks.
- Place, CTS & Routing.
- Solve setup & hold violations.
- Sign-off extraction (SPEF/QUANTUS) , timing (TEMPUS), Power analysis VOLTUS).
- Physical verification (DRC, ERC, LVS, ANT), Logic equivalent check.

If this role is of any interest please apply directly on LinkedIn or send a copy of your CV to [email protected].

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📌 Asic physical design implementation engineer (España)
🏢 European Tech Recruit
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