Job Description Our client is expanding their DFT and
Post Silicon Validation team and is looking for Senior and Lead DFT
and Post Silicon Validation Engineers to support complex SoC and
chiplet development. In this role, you will contribute to or own
DFT implementation, test strategy and post silicon validation
activities. You will work closely with design, validation,
packaging, operations, external IP providers and EDA vendors to
deliver high quality SoCs or SiPs for production. The Senior role
is focused on hands on DFT and test execution. The Lead role owns
strategy, team direction and delivery. Location : Barcelona, Spain
- Hybrid Responsibilities: As a Senior / Lead DFT and Post Silicon
Validation Engineer, your broad responsibilities will include but
are not limited to: Senior DFT and Post Silicon Validation Engineer
• Define and implement DFT architectures • Insert DFT features such
as scan chains, BIST and JTAG • Optimize DFT methods to reduce test
time, cost and quality risk • Develop test plans and test
strategies at silicon, package and system level • Define automated
test solutions for production and characterization • Ensure test
coverage from pre silicon to production • Support yield analysis
and post silicon test optimization • Work with design, validation,
packaging and operations teams • Support process improvement across
test and production Additional Responsibilities for Lead DFT and
Post Silicon Validation Engineer • Lead and mentor the DFT and Post
Silicon team • Own DFT implementation strategy and execution •
Provide technical direction and align work with company goals •
Coordinate planning, milestones and delivery • Drive improvements
in DFT methodology, cost reduction and yield quality • Act as the
main escalation point for DFT and post silicon challenges
Requirements:



Senior DFT and Post Silicon Validation Engineer • 8
plus years of related experience • Bachelor, Master or PhD in
Computer Science, Electrical Engineering or related field •
Experience with tape outs of high performance SoCs or SiPs • Strong
background in post silicon test optimization and yield analysis •
Experience defining test strategies for production • Proficiency in
RTL and testbench development using SystemVerilog and Verilog •
Strong scripting skills, Shell, Tcl or Python • Experience with
Tessent and SSN methods is a plus • English level C1 Additional
Requirements for Lead DFT and Post Silicon Validation Engineer •
Proven ability to lead DFT or post silicon teams • Experience
owning DFT implementation for complex SoCs or SiPs • Ability to
coordinate with EDA vendors, IP providers and internal teams •
Strong leadership and technical decision making skills Preferred /
Valued knowledge: Experience working with RISC V architecture is
highly valued, especially within processor, SoC, RTL, verification,
firmware, software, PCIe, DDR, PCS, DFT, Physical Design or
hardware environments. What’s in it for you? Our client offers an
exciting, challenging role in a collaborative, dynamic environment.
The right person will find many career growth opportunities in
their company, whether you want to advance your technical skills or
aspire to leadership in the future. Benefits: Versátil working
hours (office open between 7 AM and 9 PM, employees manage their
own schedule) Hybrid working model One week per year work from
anywhere 25 days annual leave plus December 24 and 31 €150 per
month food allowance (≈ €1800 per year additional compensation)
Private medical insurance One time relocation bonus paid with the
first salary Support with housing search through an agency Visa
support if required Relocation support for family Virtual shares
Language classes (Spanish, English, Catalan) Tax
incentive

📌 DFT and Post Silicon Validation Engineer (Senior /Lead) (Cataluña)
🏢 Hireroo
📍 Cataluña