Job Description

Our client is expanding their Verification Team and is looking for Mid, Senior and Lead Coherency Verification Engineers with strong background in microprocessor architecture and coherent systems.

In this role, you will verify RTL designs and validate coherency mechanisms across complex processor and SoC environments. You will work closely with architecture and RTL teams to ensure correct system behavior across cache, interconnect, memory ordering and CHI based interactions.

Location: Barcelona, Spain - Hybrid
Employment Type: Full time

Responsibilities:

As a Coherency Verification Engineer, your broad responsibilities will include but are not limited to:

Mid / Senior Coherency Verification Engineer

• Verify complex RTL designs according to architecture specifications
• Develop and maintain verification environments using SystemVerilog and UVM
• Manage regression environments using scripting and automation tools
• Perform block, subsystem and top level verification
• Apply formal and dynamic verification methods
• Analyze and debug simulation results
• Validate cache coherency mechanisms and system interactions
• Work closely with architecture and RTL design teams

Additional Responsibilities for Lead Coherency Verification Engineer

• Lead coherency verification strategy for assigned areas
• Define coverage goals and verification planning for coherent systems
• Coordinate debug and closure across architecture, RTL and verification teams
• Mentor engineers working on coherency related verification
• Own escalations for complex coherency issues

Requirements:

Mid / Senior Coherency Verification Engineer

• Experience with FPGA or ASIC,



mainly RTL and SoC
• Strong proficiency in SystemVerilog and UVM
• Experience with simulation and regression tools
• Experience with formal and dynamic verification methods
• Experience verifying coherent systems
• Knowledge of CHI protocol
• Understanding of cache structures and parameters
• Knowledge of scripting languages, Python, Perl, Bash or Tcl
• Knowledge of Git or SVN
• English level C1
• Master or PhD in Electronics, Computer Engineering or related field preferred

Lead Coherency Verification Engineer

• Strong experience owning coherency verification scope
• Strong knowledge of memory consistency, ordering and virtual memory
• Ability to lead planning, coverage closure and debug
• Strong communication with architecture teams

Preferred / Valued knowledge:
• Experience working with RISC V architecture is highly valued, especially within processor, SoC, RTL, verification, firmware, software, PCIe, DDR, PCS, DFT, Physical Design or hardware environments.

What’s in it for you?

Our client offers an exciting, challenging role in a collaborative, dynamic environment. The right person will find many career growth opportunities in their company, whether you want to advance your technical skills or aspire to leadership in the future.

Benefits:

- Versátil working hours ( You can work between 7 AM and 7 PM )

- Hybrid model, one day remote per week

- One week per year work from anywhere

- 25 days annual leave plus additional December 24 and 31

- Private medical insurance

- Relocation package including flight, visa support + first month accommodation

- Relocation support for family

- Virtual shares

- Spanish language classes

📌 Coherency Verification Engineer (Mid / Senior / Lead) (Barcelona)
🏢 Hireroo
📍 Barcelona