ppbAsic Verification Lead /b /p pIn this role, you will play a key part in verifying complex ASIC architectures used in Bull’s high‑end and exascale servers. You will drive verification strategy, lead UVM‑based methodologies, and work closely with architecture and design teams to ensure the reliability and performance of advanced semiconductor designs. /p h3Responsibilities /h3 ul liAcquire knowledge of the architecture and microarchitecture of the ASIC by studying specifications and interacting with the architecture and logical design teams. /li liParticipate in defining overall verification strategies and methodologies, and the required simulation environments. Develop, maintain and publish verification specifications. /li liWrite and perform closely test plans with the logical design team. /li liDevelop coverage models and verification environments using UVM-SystemVerilog / C++. /li liMonitor, analyze and debug simulation errors. /li liMonitor and analyze simulation coverage results to improve tests accordingly thereby achieving coverage targets on time. /li liSubmit recommendations on tools and methodologies to develop to improve productivity.



/liliMentor junior engineers on how to produce a maintainable and reusable code across projects. /li /ul h3What we’re looking for /h3 h3Education /h3 ul liExperience: 8+ years /li liEducation: Bachelor's Degree (BE / BTech) or Master's Degree (ME / MTech) /li /ul h3Competences Skills /h3 ul liIntegrating ASIC functional verification team. /li liASIC developed include network controller, router and cache coherence controller targeting Bull high-end servers and Bull high-performance ("big data" and "exascale") servers. /li liUsing "Constraint‑Random, Coverage‑Driven" functional verification methodologies underlying UVM verification framework to ensure full and effective verification of complex ASIC. /li liParticipated in the successful verification of a complex SoC or ASIC. /li liMastering UVM or equivalent verification methodology. /li /ul h3Location /h3 ul liMadrid or Barcelona (or remote within Spain) /li liFlexible Work Schedule: Half day Fridays and an intensive summer workday supporting work life balance. /li liLearning and Growth: Opportunities to work with advanced AI technologies in an innovative and supportive RD environment. /li /ul /p #J-18808-Ljbffr

📌 ASIC Verification Lead (Madrid)
🏢 Atos
📍 Madrid