ppbAre you an experienced DFT Engineer looking for your next challenge? /b /ppAion Silicon is actively building a pipeline of talented engineers for future opportunities, and we’d love to hear from skilled professionals who are passionate about Design for Test. /ppWith design centers across the bUK, Spain, Hyderabad, and Morocco /b, we offer the flexibility to base this role in any of our general locations. If you’re interested in exploring future opportunities with us, please click the link below to apply and register your interest. /ph3Purpose of Role /h3pTo lead and own chip-level Design for Test execution, driving DFT delivery from architecture definition through pattern generation and silicon bring-up. This role ensures high-quality DFT implementation, effective debug and timing closure across test modes, and provides technical leadership within the team, while acting as a key stakeholder interface to ensure predictable and successful delivery. /ph3Responsibilities /h3ulliLead DFT strategy definition, implementation of DFT structures, and verification to ensure chip-level testability and project success. /liliServe as an expert in DFT, providing industry-leading technical guidance in specialized areas. /liliSolve highly complex problems and provide innovative solutions to technical challenges. /liliDefine, plan, and lead large, technically complex projects, ensuring alignment with program goals. /liliApply judgment in interpreting results, conducting quantitative analysis, and driving data-informed decisions. /liliMaintain and promote high-quality outputs across the team, ensuring best practices and consistency. /liliCollaborate effectively with team members and engineering management,



fostering a productive and engaged team environment. /liliMentor junior engineers and provide leadership across multi-disciplinary project teams. /liliContribute to technical thought leadership through white papers, internal/external presentations, and participation in sales support activities, such as Statements of Work. /liliListen to customer feedback, identify opportunities, and work with the Business Team to translate technical insights into business growth. /li /ulh3Qualifications /h3ulliA degree/masters or PhD in a relevant subject /liliTypically 10+ years of experience in Design for Test (DFT) engineering. /liliExpertise with DFT tools from Siemens or Synopsys, including IJTAG, scan compression, MBIST, SSN, boundary scan, and repair implementation. /liliStrong experience in ATPG and test coverage improvements, pattern simulation (Zdel/SDF), and diagnosing ATE failures and silicon bring-up. /liliSolid understanding of DFT principles and architecture, with proven experience designing complex chip-level DFT solutions. /liliRecognized as a problem solver with the ability to lead or contribute effectively within a DFT team. /liliDemonstrated capability to lead DFT design projects as an expert or provide industry‑leading expertise in specific DFT areas. /liliStrong project management skills, with the ability to evaluate issues, define solutions, and drive project delivery. /li /ulh3Attributes /h3ulliTeam organisation and ability to set and change priorities quickly /liliAbility to motivate a team to work under pressure /liliOrganisation and problem‑solving skills /liliExcellent attention to details /liliSelf‑motivated /liliAbility to quantify risks and estimate engineering effort /li /ul /p #J-18808-Ljbffr

📌 Principal DFT Engineer (Barcelona)
🏢 Aion Silicon
📍 Barcelona