ppAre you looking for an innovative and consolidated place for your professional development? GMV is an experienced technology group and… /p pWe are expanding our teams in the bGNSS‑User Segment Navigation /b unit to take on bprojects /b related to breceivers technology /b. /p pWe’ll get to the point; we’ll tell you what’s not on the web. If you want to know more about us go to GMV website. /p h3WHAT CHALLENGE WILL YOU BE TAKING ON? /h3 pAs part of the bGMV Receivers team /b, you will have a key role in projects related to receiver technology, contributing to the development of projects and products with strong involvement in RD activities. /p pYou will participate in bmigrating an architecture /b currently implemented on Xilinx MPSoC / FPGA to an ASIC solution. Additionally, you will have the opportunity to work on the analysis of the existing design, identification of reusable blocks, adaptation of the hardware architecture, and definition of the ASIC implementation flow. /p pYour bmain tasks /b would be: /p ul liDefine and evolve the target architecture for ASIC. /li liDevelop and adapt RTL blocks (VHDL/Verilog/SystemVerilog). /li liAnalyze and optimize internal interfaces (buses, memories, synchronization, clocks, and resets). /li liParticipate in functional verification, simulation, and design debugging. /li liContribute to the ASIC flow: synthesis, timing analysis, CDC/RDC, DFT, and design closure. Document architecture, technical decisions, and validation results. /li /ul h3WHAT DO WE NEED IN OUR TEAM? /h3 pFor this role, we are looking for graduates in bElectronic Engineering, Telecommunications, Computer Science, or similar /b, with a specialization in the field of bdigital hardware programming /b. /p pAdditionally,



we are seeking profiles with knowledge of bdigital RTL design /b, bFPGA, SoC or MPSoC architectures /b, internal bbuses /b, bIP integration /b, and functional verification; as well as previous experience in bASIC flow /b and handling bsimulation and synthesis tools /b. /p pWe will also bvalue previous knowledge /b of STA, DFT, scan, low‑power, UPF, floorplanning or backend; verification with SystemVerilog, UVM, assertions or cocotb; embedded ARM/RISC‑V processors and hardware/software partitioning; and experience with Synopsys, Cadence, Siemens EDA, Vivado, or Vitis tools. /p h3WHAT DO WE OFFER? /h3 pHybridworking model and 8 weeks per year of teleworking outside your usual geographical area. /p pFlexible start and finish times, and intensive working hours Fridays and in summer. /p pPersonalized career plan development, training and language learning support. /p pNational and international mobility. Do you come from another country? We can offer you a relocation package. /p pCompetitive compensation with ongoing reviews, versátil compensation and discount on brands. /p pWellbeing program: Health, dental and accident insurance; free fruit and coffee, physical, mental and financial health training, and much more! /p pIn our recruitment processes you will always have telephone and personal contact, face‑to‑face or online, with our talent acquisition team. In addition, bank transfers and bank cards will never be requested. If you are contacted through any other process, please write to our team at /p pWe promote equal opportunities in recruitment, and we are committed to inclusion and diversity. /p h3WHAT ARE YOU WAITING FOR? JOIN US /h3 pIf you have any questions please do not hesitate to contact bCarolina Barber Caso /b, in charge of this vacancy. /p /p #J-18808-Ljbffr

📌 Embebbed software engineer (Madrid)
🏢 Gmv Spain
📍 Madrid