ph3Company Description: /h3 pAistech Space is focused on generating affordable, recurrent, high-resolution thermal imagery of the planet to provide a new perspective of Earth’s changing resources. The company is based in Barcelona and aims to revolutionize remote sensing for environmental monitoring and resource management. /p h3What you will do: /h3 pAistech Space is seeking an expert FPGA Design Engineer to lead the development of our next-generation image acquisition and processing payloads. You will be the architect of the “digital brain” of our systems, transforming raw high-speed sensor data into actionable insights using cutting-edge VHDL logic and hardware acceleration. /p pThis role is not just about writing code; it is about managing the entire data lifecycle—from the physical high-speed pins of the FPGA to the integration of AI engines and DMA streaming to memory. You will work at the intersection of hardware and high-level software, ensuring our systems are fast, synchronized, and reliable in demanding environments /p pIn this role, you are expected to work as a team, functioning as an agile, highly collaborative unit focused on short, client-driven development iterations. /p pYou will also be responsible for following internal standards and good practices in terms of project management, documentation, and time management, adopting an agile approach in your daily work. /p pThe key objectives to be achieved in this position are: /p ul liUnderstand Aistech Space mission objectives. /li libXilinx RTL Development: /b Design and optimize modular VHDL code for Xilinx 7-Series, UltraScale+, and Versal Adaptive SoCs. /li libHigh-Speed I/O Connectivity: /b Implement and debug high-speed transceivers (GTH/GTY) for protocols such as MIPI CSI-2, PCIe Gen3/4, and 10G/25G Ethernet. /li libAdvanced Data Path: /b Architect low-latency data movement using AXI4-Stream,



AXI SmartConnect, and Xilinx Video DMA (VDMA) or DataMover IPs. /li libAI Engine Integration: /b Deploy and optimize neural networks using the Vitis AI flow, integrating DPU (Deep Learning Processor Unit) cores into the FPGA fabric. /li libMemory Management: /b Configure and optimize hardened DDR4/LPDDR4 memory controllers to handle multi-stream 4K/8K video buffering. /li libTiming Closure: /b Author complex XDC constraints, manage multiple clock domains using MMCM/PLLs, and achieve timing closure on high-utilization designs. /li libVerification Debug: /b Perform hardware-in-the-loop debugging using Vivado ILA (Integrated Logic Analyzer) and Vitis Analyzer. /li liWrite articles regarding different areas of interest to be published in our Aistech News magazine and on our website blog. /li liActively engage in the development of documentation to build out the company procedures and specification manuals. /li liFollow your curiosity to suggest new ideas to make our products and processes better. /li /ul h3Who you are: /h3 h3Must: /h3 ul liDegree: BSc/MSc in Electronics, Telecommunications, or similar. /li libVHDL Expert: /b Deep understanding of Xilinx-specific RTL optimization (utilizing DSP48 slices, Block RAM, and UltraRAM efficiently). /li libAMD Toolchain Expert: /b Proficiency in Vivado Design Suite, Vitis Unified Software Platform, and Petalinux. /li libIP Integration:



/b Extensive experience with Xilinx IP Integrator and the AXI4 protocol family (Memory Mapped, Stream, and Lite). /li libHigh-Speed Hardware: /b Experience with SerDes calibration, eye-diagram analysis, and high-speed PCB constraints. /li libDMA/Data Transfer: /b Proven experience implementing Scatter-Gather DMA for high-bandwidth sensor data. /li libVerification Skills: /b Experience with advanced simulation environments (UVVM, OSVVM, or UVM) and self-checking testbenches. /li libSimulation: /b Experience with Xilinx Simulator (XSIM) or third-party tools like ModelSim/Questa using Xilinx Verification IP (VIP). /li libScripting: /b Proficiency in Tcl for Vivado automation and Python for data analysis. /li liFluent in English. /li /ul h3Nice to have: /h3 ul libVersal Experience: /b Knowledge of Versal AI Engines (AIE) and the Programmable Network on Chip (NoC). /li libHLS Knowledge: /b Familiarity with Vitis HLS (C/C++ to RTL synthesis) for rapid IP development. /li libSpace/High-Reliability Experience: /b Familiarity with SEU (Single Event Upset) mitigation techniques and radiation-hardened design philosophies. /li /ul h3What You’ll Gain by Joining Us /h3 ul liBe part of a passionate, collaborative, and respectful team. /li liEnjoy a stable, permanent contract with a fast-growing company. /li liFlexible working hours and hybrid work: 6 days/month from home. /li liCompetitive salary and versátil retribution through Cobee. /li liFree access to paddle tennis courts and an on-site gym. /li liDaily fresh fruit and coffee to keep you energized. /li liWork in an international, diverse environment. /li li23 vacation days, plus Birthday, December 24 31 off. /li /ul pbTo be considered for this position, you must already have the legal right to work in the European Union. We are unable to provide visa sponsorship. /b /p /p #J-18808-Ljbffr

📌 FPGA Designer Engineer (Barcelona)
🏢 Aistech Space
📍 Barcelona