The TMRW Foundation SILICON is seeking a skilled Digital IC Designer to develop, simulate, and verify complex digital ICs using a Cadence-centric flow. You will implement RTL in VHDL/Verilog, perform functional verification, and drive synthesis and physical implementation tasks across floorplanning, placement, and routing.
Responsibilities include timing closure with Tempus, DRC/LVS verification, and close collaboration with architects, analog designers, and layout engineers.
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📌 Senior Digital Ic Designer - Rtl, Verilog, Cadence (Madrid)
🏢 TMRW
📍 Madrid
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