ph3Responsibilities /h3 pYou will join the receiving team to lead FPGA/SoC based hardware design projects, architecture definition, junior team mentoring and critical system optimization. /p pFunctions: /p ul liArchitecture definition /li liCoding in VHDL/Verilog /li liAdvanced verification (SystemVerilog/UVM) /li liResource optimization /li liHW/SW interfaces definition /li liMentoring of junior engineers /li liTechnical documentation /li /ul h3Qualifications /h3 pHardware engineering experts with experience in FPGA development, advanced VHDL/Verilog, synthesis and verification tools (Vivado, Quartus, ModelSim, QuestaSim), modular/IP design, timing optimization, high speed interfaces, C++ or Rust, Python, GIT. /p pKnowledge of Process Automation, signal processing, HDL coder, soft core processors, standards (DO-254, ECSS) and ASIC design would be an asset. /p pAvailability for travel for meetings or tests in European countries is required.



/p h3What We Offer /h3 pHybrid working model and 8 weeks per year of teleworking outside your usual geographical area. /p pFlexible start and finish times, and intensive working hours Fridays and in summer. /p pPersonalized career plan development, training and language learning support. /p pNational and international mobility. If you come from another country we can offer a relocation package. /p pCompetitive compensation with ongoing reviews, adaptable compensation and discount on brands. /p pWellbeing program: Health, dental and accident insurance; free fruit and coffee; physical, mental and financial health training, and much more! /p pWe promote equal opportunities in recruitment and are committed to inclusion and diversity. /p pContact: Ignacio Martínez de Salinas. /p /p #J-18808-Ljbffr

📌 Senior Hardware Design Engineer (FPGA) (Tres Cantos)
🏢 GMV
📍 Tres Cantos