ppWe are seeking an experienced Senior Verification Engineer with 8+ years of industry expertise in /ppdigital design verification. The adecuado candidate will have a strong background in SystemVerilog and /ppUVM, with proven experience in block-level, subsystem, and top-level verification. Knowledge of /ppboth formal and dynamic verification methodologies is essential. /ppIn this role, you will work within the Verification Team to ensure the correctness and /ppfunctionality of complex microprocessor architectures at the RTL level. You will develop and apply /ppadvanced verification methodologies, build testbenches, run simulations, and collaborate closely /ppwith design teams to deliver high-quality, production-ready designs. /ph3Requirements /h3ulliMaster’s or PhD in Computer Science,



Electrical Engineering, or a related field /liliProficiency in SystemVerilog and UVM /lili8+ years of relevant industry experience /liliHands-on experience with simulation tools and regression management /liliFamiliarity with revision control tools (git, svn) /liliProven experience in block-level, subsystem, and top-level verification /liliBackground in both formal and dynamic verification methodologies /liliExcellent problem-solving skills and attention to detail /liliStrong communication and teamwork abilities /li /ul /p #J-18808-Ljbffr

📌 Senior Design Verification Engineer (Barcelona)
🏢 Beagle
📍 Barcelona