Job Description Our client is expanding their RTL team
and is looking for Mid / Senior RTL and Microarchitecture Engineers
with strong experience in processor architecture, acceleration or
compute intensive digital design. This role is focused on design
areas such as matrix multiplication, neural processing, near data
processing, systolic arrays, SIMD and integer or floating point
arithmetic. You will translate architecture and microarchitecture
requirements into RTL implementation, working closely with
architecture, verification and physical design teams. Location :
Barcelona, Spain - Hybrid Responsibilities: As a RTL /
Microarchitecture Engineer, Matrix / Neural Processing (Mid /
Senior), your broad responsibilities will include but are not
limited to: • Design and implement RTL modules in Verilog based on
architecture and microarchitecture specifications • Contribute to
processor or accelerator components related to matrix
multiplication and neural processing • Work on near data
processing, systolic arrays, SIMD or arithmetic units where
required • Translate architecture concepts into efficient and
scalable RTL designs • Collaborate closely with architecture,
verification and physical design teams • Develop and use scripts to
support design, automation and integration tasks • Participate in
design reviews and technical discussions • Support debug,
integration and timing related design closure needs Requirements:
Mid RTL / Microarchitecture Engineer • 4 to 7 years of relevant
industrial experience in RTL or microarchitecture • Strong
knowledge of Verilog • Experience translating architecture
requirements into RTL • Experience with scripting for automation




and design support • Understanding of digital design, timing and
integration workflows • English level C1 • Bachelor, Master or PhD
in Computer Science, Computer Engineering or related field Senior
RTL / Microarchitecture Engineer • 8 plus years of relevant
industrial experience in RTL or microarchitecture roles • Strong
background in processor microarchitecture and system level
understanding • Experience with compute acceleration, SIMD, matrix
operations or arithmetic datapaths is highly relevant • Ability to
own complex design blocks from concept to RTL implementation •
Strong communication with architecture, verification and physical
design teams Preferred / Valued knowledge Experience working with
RISC V architecture is highly valued, especially within processor,
SoC, RTL, verification, firmware, software, PCIe, DDR, PCS, DFT,
Physical Design or hardware environments. What’s in it for you? Our
client offers an exciting, challenging role in a collaborative,
dynamic environment. The right person will find many career growth
opportunities in their company, whether you want to advance your
technical skills or aspire to leadership in the future. Benefits:
Adaptable working hours (office open between 7 AM and 9 PM,
employees manage their own schedule) Hybrid working model One week
per year work from anywhere 25 days annual leave plus December 24
and 31 €150 per month food allowance (≈ €1800 per year additional
compensation) Private medical insurance One time relocation bonus
paid with the first salary Support with housing search through an
agency Visa support if required Relocation support for family
Virtual shares Language classes (Spanish, English, Catalan) Tax
incentive

📌 RTL / Microarchitecture Engineer, Matrix / Neural Processing(Mid / Senior) (Cataluña)
🏢 Hireroo
📍 Cataluña