ppThis Full time on site position offers great opportunities for career growth. /ph3Main function and scope: /h3ulliOwn and execute backend implementation flows for ASIC and/or FPGA designs. /liliPerform logic synthesis, constraint development, optimization, and design quality checks. /liliRun place and route flows, including floorplanning, placement, clock tree synthesis, routing, and physical optimization. /liliDrive static timing analysis and timing closure across multiple modes and corners. /liliAnalyze and resolve timing, congestion, area, power, and signal integrity issues. /liliDevelop, review, and maintain timing constraints, including SDC/XDC files. /liliSupport backend sign-off activities such as timing, power, DRC/LVS, CDC/RDC, and equivalence checking, depending on project scope. /liliSupport mixed-signal integration activities, including coordination between analog and digital implementation flows. /liliWork with analog designers on floorplanning, pin planning, power domains, guard rings, keep-outs, substrate noise considerations, and analog/digital interface constraints. /liliSupport the integration of analog macros, hard IP blocks, memories, PLLs, ADCs, DACs, sensors, or other mixed-signal IP. /liliCollaborate with frontend RTL designers to improve implementation quality and resolve design issues. /liliWork with FPGA flows including synthesis, implementation, timing analysis, bitstream generation, and hardware bring-up support. /liliContribute to automation scripts and flow improvements using Tcl, Python, Bash, or similar scripting languages. /liliParticipate in design reviews and provide technical input on architecture, feasibility, performance, power, and area trade-offs. /liliSupport requirements analysis, traceability,



and verification alignment where applicable. /li /ulh3Required experience and candidate profile: /h3ulliTelecommunications engineering, electronic engineering or equivalent. /liliA master in micro-electronics or applicable experience in the field. /lili+5 years of experience in back-end ASIC/FPGA design /li /ulh3Technical Requirements: /h3pTraining / specific knowledge required in: /pulliProfessional experience in ASIC and/or FPGA backend implementation. /liliStrong knowledge of digital implementation flows, including synthesis, place and route, and timing closure. /liliExperience with static timing analysis and constraint definition. /liliFamiliarity with industry-standard EDA tools for ASIC and/or FPGA implementation, such as Synopsys, Cadence, Siemens EDA, Xilinx/AMD Vivado, or Intel Quartus. /liliGood understanding of clocking, reset strategies, timing exceptions, CDC considerations, and low-power design concepts. /liliAbility to debug timing, congestion, utilization, routing, and implementation issues. /liliUnderstanding of mixed-signal design integration challenges, especially analog/digital interfaces, floorplanning constraints, power integrity, noise coupling, and physical verification implications. /liliScripting experience with Tcl, Python, Bash, Perl, or similar. /li /ulh3Nice-to-have training / specific knowledge:



/h3ulliExperience with frontend RTL design using VHDL, Verilog, or SystemVerilog. /liliExperience supporting mixed-signal ASIC designs with analog macros or custom IP. /liliExperience with requirements management, traceability, and requirements-based verification. /liliKnowledge of safety-critical or high-reliability development flows, such as aerospace, automotive, defense, or space applications. /liliFamiliarity with ECSS, or similar standards. /liliExperience with formal verification, linting, CDC/RDC analysis, logic equivalence checking, or power analysis. /liliExperience with DRC/LVS debugging, parasitic extraction, IR drop analysis, EM analysis, or physical sign-off. /liliExperience with FPGA prototyping, lab debugging, board bring-up, or hardware validation. /liliKnowledge of high-speed interfaces, embedded processors, SoCs, DSP blocks, memory controllers, PLLs, ADCs, DACs, or sensor interfaces. /liliExperience developing reusable implementation flows and automation infrastructure. /li /ulpThe position is located at our headquarters in Madrid, at Calle Serrano Galvache, 56. /ppWe're looking for curious, creative, tenacious and collaborative people, eager to do things and unafraid to tackle challenges in order to contribute to improving the society in wich we live. /ppThink Big, Do the Job Enjoy Life /ppAt ARQUIMEA, we value diversity and inclusion. /ppWe do not discriminate on the basis of race, color, religion, gender, sexual orientation, gender identity, national origin, age, disability, or other protected factors by law. /ppAll candidates will be considered equally based on their skills and experience. /p /p #J-18808-Ljbffr

📌 Backend ASIC/FPGA Engineer at ARQUIMEA (Madrid)
🏢 Arquimea
📍 Madrid