ph3Company Description: /h3 pAistech Space is focused on generating affordable, recurrent, high-resolution thermal imagery of the planet to provide a new perspective of Earth’s changing resources. The company is based in Barcelona and aims to revolutionize remote sensing for environmental monitoring and resource management. /p h3What you will do: /h3 pAistech Space is seeking an expert FPGA Verification Validation Engineer to build, lead, and execute the verification strategy for our next-generation image acquisition and processing payloads. Instead of designing the logic fabric, your primary mission will be to ensure the absolute reliability, timing compliance, and functional flawless performance of the “digital brain” of our systems before flight deployments. /p pYou will architect and build advanced simulation frameworks and hardware-in-the-loop (HIL) testing infrastructures from scratch. Acting as the ultimate quality gatekeeper, you will test and push VHDL logic, AI engine integrations, and high-speed data paths to their limits, ensuring our satellite payloads operate with 100% predictability in the harsh environment of space. /p pIn this role, you are expected to work as a team, functioning as an agile, highly collaborative unit focused on short, client-driven development iterations, while enforcing internal standards and good practices in project management, documentation, and time management. /p h3The key objectives to be achieved in this position are: /h3 ul libUnderstand Mission Objectives /b: Align FPGA validation protocols deeply with overall Aistech Space mission objectives. /li libAdvanced Verification Frameworks: /b Design and implement self-checking testbenches and advanced simulation environments utilizing UVVM, OSVVM, or UVM to comprehensively verify complex VHDL designs. /li libToolchain Simulation Mastery: /b Run exhaustive functional and timing simulations using Xilinx Simulator (XSIM) or third-party tools like ModelSim/Questa, leveraging Xilinx Verification IP (VIP).



/li libHigh-Speed I/O Connectivity Testing: /b Test, characterize, and debug high-speed transceivers (GTH/GTY) and critical interfaces like MIPI CSI-2, PCIe Gen3/4, and 10G/25G Ethernet. /li libData Path Validation: /b Formally verify low-latency data movement pipelines involving AXI4-Stream, AXI SmartConnect, and Xilinx Video DMA (VDMA) or DataMover IPs. /li libHardware-in-the-Loop (HIL) Debugging: /b Lead bench-level and flight-model hardware verification campaigns using Vivado ILA (Integrated Logic Analyzer), Vitis Analyzer, and standard laboratory equipment (oscilloscopes, logic analyzers). /li libTiming Closure Verification: /b Critically review complex XDC constraints, analyze multi-clock domains managed by MMCM/PLLs, and validate timing margins on high-utilization designs. /li libAI Engine Memory Validation: /b Verify the robust deployment of neural networks through Vitis AI flow and validate hardened DDR4/LPDDR4 memory controllers under multi-stream 4K/8K video loads. /li libAutomation Strategy: /b Drive verification efficiency by developing automated testing script suites in Tcl for Vivado and Python for data/test results analysis. /li libDocumentation Reporting: /b Actively engage in the development of comprehensive validation plans, test reports, and specification manuals to build out company procedures, and author technical articles for Aistech News or the company blog. /li /ul h3Who you are: /h3 h3Must: /h3 ul libDegree /b: BSc/MSc in Electronics, Telecommunications, Computer Science, or similar. /li libVerification Expertise /b:



Proven professional experience in advanced FPGA verification methodologies (UVVM, OSVVM, or UVM) and building modular, scalable testbenches. /li libAMD Toolchain Proficiency /b: Solid experience within the AMD/Xilinx eco-system, including Vivado Design Suite, Vitis Unified Software Platform, and associated simulation environments. /li libProtocol Familiarity: /b Strong working knowledge of the AXI4 protocol family (Memory Mapped, Stream, and Lite) and structural design verification patterns. /li libScripting Power: /b Fluency in Python for test automation and scripting, as well as Tcl for tool workflow automation. /li libFluent in English: /bExcellent communication skills for global, multidisciplinary collaboration. /li /ul h3Nice to have: /h3 ul libVersal HLS Exposure: /b Familiarity with validating Versal AI Engines (AIE), Programmable Network on Chip (NoC), or testing Vitis HLS generated blocks. /li libHigh-Reliability Industry Experience /b: Prior exposure to NewSpace, aerospace, or defense industries, including knowledge of Single Event Upset (SEU) mitigation and radiation-hardened testing philosophies. /li libHardware Bring-up: /b Basic experience with SerDes calibration and eye-diagram analysis. /li /ul h3What You’ll Gain by Joining Us /h3 ul liBe part of a passionate, collaborative, and respectful team. /li liEnjoy a stable, permanent contract with a fast-growing company. /li liFlexible working hours and hybrid work: 5 days/month from home. /li liCompetitive salary and versátil retribution through Cobee. /li liFree access to paddle tennis courts and an on-site gym. /li liDaily fresh fruit and coffee to keep you energized. /li liWork in an international, diverse environment. /li li23 vacation days, plus Birthday, December 24 31 off. /li /ul pTo be considered for this position, you must already have the legal right to work in the European Union. We are unable to provide visa sponsorship. /p /p #J-18808-Ljbffr

📌 FPGA Verification & Validation Engineer (Barcelona)
🏢 Aistech Space
📍 Barcelona