h3Senior Verification Engineer – Drive Quality in Next‑Gen RISC‑V CPUs (UVM/SystemVerilog) /h3 h3Overview /h3 pAt Akuaro, we are proudly leading the recruitment process for our partner — a European deep-tech company redefining what’s possible in high-performance computing and digital infrastructure. Specialized in cutting-edge RISC-V systems and backed by major innovation initiatives, our partner is assembling a world-class engineering team in Barcelona. They are now seeking a bSenior Verification Engineer /b with expertise in SystemVerilog and UVM to ensure their next generation of high-performance silicon meets the highest quality standards. /p pbContract: /b Permanent – Internal team of our partner /p h3Why This Role Is Unique /h3 ul liJoin the forefront of Europe’s semiconductor revolution in CPU design and verification. /li liVerify bcutting-edge RISC-V processors /b destined for high-performance computing applications. /li liUse the latest badvanced verification methodologies /b (UVM, formal verification) on complex, modern microarchitectures. /li libFull-cycle ownership /b – contribute from block-level verification to full system validation. /li liInfluence design quality from day one; your work directly impacts first-silicon success. /li /ul h3What You’ll Be Doing /h3 ul liDevelop and maintain bUVM-based testbenches /b for complex digital designs (CPU cores, SoC blocks). /li liDefine and implement comprehensive bverification plans /b, covering all features and corner cases. /li liWrite and run directed and bconstraint-random tests /b to validate functionality and performance.



/li liImplement checkers and monitors in SystemVerilog to verify correctness of microarchitectural features. /li liExecute extensive simulations and regression suites; analyze waveform dumps to debug failing tests. /li liUse bcoverage-driven verification /b (functional and code coverage) to measure progress and target gaps. /li liApply bformal verification /b techniques to prove critical properties and catch corner-case bugs. /li liAutomate workflows with scripting (Python/Perl/Bash/TCL) for regression management and result analysis. /li liCollaborate closely with design and RTL teams to review specifications, discuss bugs, and drive fixes to closure. /li /ul h3What You Bring /h3 ul liMaster’s or PhD in Electronic Engineering, Computer Engineering, or related field. /li lib8+ years /b of experience in digital design verification. /li liProven expertise in bSystemVerilog /b and bUVM /b for complex ASIC/SoC verification. /li liStrong scripting skills (Python, Perl, Bash, or Tcl) to automate verification flows and data analysis. /li liHands-on experience with simulation tools (e.g., ModelSim, VCS, Xcelium) and waveform debugging. /li liFamiliarity with coverage metrics and bcoverage closure /b strategies.



/li liKnowledge of bformal verification /b tools/methods (property checking, equivalence checking) is a plus. /li liExperience verifying both bblock-level modules /b and full bsystem-level integrations /b. /li liProficiency with version control systems (Git, SVN) in collaborative engineering projects. /li liExcellent problem-solving abilities and battention to detail /b – able to root-cause intricate bugs. /li liStrong communication and teamwork skills, collaborating effectively with cross-functional teams. /li libEnglish fluency (C1 or higher) /b. /li /ul h3What’s in It for You /h3 ul libFlexible working hours /b – Focus on outcomes, not just schedules. /li libCompetitive compensation /b – Recognizing your expertise and impact. /li libLearning-driven culture /b – Work with top-tier engineers on cutting-edge projects; continuous growth encouraged. /li libVisa sponsorship /b – Open to international talent; relocate to a vibrant tech hub. /li libCandies, coffee, and free Spanish lessons /b – Enjoy a welcoming office culture while settling into life in Barcelona. /li libBarcelona HQ /b – Where tech innovation meets Mediterranean lifestyle. /li libReady to Build the Future of Chips in Europe? /b /li /ul pIf you’re passionate about verification and want to play a key role in one of Europe’s most exciting deep-tech projects, we want to hear from you. /p pbApply now /b — Akuaro is exclusively managing this hiring process for our partner. Let’s connect and explore this opportunity together. /p #J-18808-Ljbffr

📌 Senior Verification Engineer – Drive Quality in Next‑Gen RISC‑V CPUs (UVM/SystemVerilog) (Barcelona)
🏢 Akuaro
📍 Barcelona