Responsibilities
Habilidades, experiencia, cualificaciones... Si tiene el perfil adecuado para esta posibilidad, asegúrese de inscribirse hoy mismo.

You will join the receiving team to lead FPGA/SoC based hardware design projects, architecture definition, junior team mentoring and critical system optimization.

Functions:

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- Architecture definition

- Coding in VHDL/Verilog

- Advanced verification (SystemVerilog/UVM)

- Resource optimization

- HW/SW interfaces definition

- Mentoring of junior engineers

- Technical documentation

Qualifications

Hardware engineering experts with experience in FPGA development, advanced VHDL/Verilog, synthesis and verification tools (Vivado, Quartus, ModelSim, QuestaSim), modular/IP design, timing optimization, high speed interfaces, C++ or Rust, Python, GIT.

Knowledge of Process Automation, signal processing, HDL coder, soft core processors, standards (DO-254, ECSS) and ASIC design would be an asset.





Availability for travel for meetings or tests in European countries is required.

What We Offer

Hybrid working model and 8 weeks per year of teleworking outside your usual geographical area.

Flexible start and finish times, and intensive working hours Fridays and in summer.

Personalized career plan development, training and language learning support.

National and international mobility. If you come from another country we can offer a relocation package.

Competitive compensation with ongoing reviews, flexible compensation and discount on brands.

Wellbeing program: Health, dental and accident insurance; free fruit and coffee; physical, mental and financial health training, and much more!

We promote equal opportunities in recruitment and are committed to inclusion and diversity. xqbhyrx

Contact: Ignacio Martínez de Salinas.

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📌 Senior Hardware Design Engineer (FPGA) (Tres Cantos)
🏢 GMV
📍 Tres Cantos