Experteer Overview
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In this role you will contribute to verifying complex ASICs using constraint-random, coverage-driven methods within a UVM framework. You’ll collaborate with architecture and design teams to define verification strategies, build and maintain verification environments and test plans, and optimize coverage to meet targets on time. The position sits at the heart of Bull’s high‑performance computing and AI initiatives, offering exposure to exascale systems and advanced hardware/software integration. You will help shape robust verification flows that enable scalable, reliable silicon for next‑gen servers and data-intensive workloads.
Compensaciones / Incentivos
• Acquire knowledge of ASIC architecture and microarchitecture from specifications and design teams
• Define verification strategies and required simulation environments
• Develop,



maintain and publish verification specifications; define test plans with design team
• Develop verification environments, test cases, and coverage models using UVM / SystemVerilog / C++
• Track, analyze, and debug simulation errors
• Monitor and improve simulation coverage to meet targets on time
• Submit tool and methodology recommendations to boost productivity
Responsabilidades
• 3-5 years of experience
• Experience using constraint-random, xqbhyrx coverage-driven verification under UVM
• Mastery of UVM or equivalent verification methodologies
• Proficiency in simulation and coverage analysis tools
• Strong problem-solving skills and ability to root cause fixes
• Participation in verification of a complex SoC or ASIC
Requisitos principales
• Flexible Work Schedule
• Half day Fridays
• Intensive summer workday
• Learning and growth opportunities

📌 ASIC Verification Engineer (Madrid)
🏢 Atos
📍 Madrid