03 ago
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Arquimea
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Madrid
ARQUIMEA is seeking an experienced engineer to lead backend ASIC/FPGA design efforts on-site in Madrid. You will own backend flows, perform timing analysis, and drive sign-off activities while coordinating with frontend RTL teams and analog designers.
The role emphasizes deep knowledge of digital implementation, clocking strategies, and power integrity in a demanding, collaborative environment in Madrid.
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📌 Senior ASIC/FPGA Backend Engineer (Madrid)
🏢 Arquimea
📍 Madrid