03 ago
|
Intellectual Capital Resources
|
Barcelona
03 ago
Intellectual Capital Resources
Barcelona
Experteer Overview
Habilidades, experiencia, cualificaciones... Si tiene el perfil adecuado para esta oportunidad, asegúrese de inscribirse hoy mismo.
As Senior DFT and Post-Silicon Lead, you will drive DFT strategy, architectures, and post-silicon validation for complex SoCs and chiplets in package. You’ll lead cross-functional teams, work with IP providers and EDA vendors, and aim for high yield, low test time, and robust testability in mass production. The role blends leadership, technical direction, and continuous improvement to scale testing and manufacturing.
This is a high-impact, cutting-edge position at the intersection of design, test, and production excellence.
Compensaciones / Incentivos
- Lead and mentor DFT and Post-Silicon engineering teams to foster innovation and efficiency
- Define and implement DFT architectures to enhance testability, debug capabilities, and manufacturability
- Integrate DFT features (scan chains, BIST, JTAG) into designs
- Optimize DFT methods to reduce test time, costs, and improve quality and yield
- Develop and execute test plans/strategies at silicon, package, and system levels
- Design automated test solutions for production and characterization
- Ensure comprehensive test coverage from pre-silicon to mass production
- Guarantee high yield addressing chiplet complexities
- Collaborate with design, validation, packaging, and operations teams to ensure seamless testing and manufacturability
- Lead initiatives to reduce costs, improve efficiency, and enhance quality in test and production
Responsabilidades
- Multiple tape-outs of high-performance SoCs xugodme or SiPs for mass production
- Strong expertise in post-silicon test optimization and yield analysis
- Experience defining and implementing test strategies for high-volume production
- Proficiency in RTL and testbench development using SystemVerilog and Verilog
- Strong scripting skills in Shell, Tcl, and Python3
- Hands-on experience with Tessent and SSN methods integrated with leading EDA design flows for advanced technology nodes
- Bachelor (minimum)
Requisitos principales
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📌 DFT Lead (Barcelona)
🏢 Intellectual Capital Resources
📍 Barcelona