31 jul
|
Jobbydoo
|
Madrid
Capgemini Engineering in Madrid is seeking a Senior RTL Engineer to lead RTL design activities from architecture to tape-out. You will align with functional leads and backend teams to ensure timing, power, and area targets are met while driving robust design flows.
Adecuado candidates bring 8+ years in VLSI, strong Verilog/SystemVerilog or VHDL, and hands-on SoC design experience, plus scripting in Python/Perl. Excellent communication and collaboration skills are essential.
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📌 Senior RTL Engineer - Lead Microarchitecture, Flexible Hours (Madrid)
🏢 Jobbydoo
📍 Madrid