Everything we do is designed to challenge the limits of imaging and sensing technologies. We thrive on excellence in execution while having fun pushing the boundaries of what an image can express.

We offer a permanent contract with a competitive salary and career opportunity in a growing company with global coverage and ambition. There’s still a lot of work to be done. We need best‑in‑class optical designers, software, parallel computing, heterogeneous computing, and digital image processing experts.

Interested in joining photonicSENS? We are always looking for new talent!

Digital Design Verification Engineer

Digital Design Verification Engineer to help develop an innovative low‑power consumption ASIC that obtains high‑quality depth maps and images by processing real‑time video frames captured by apiCAM, our leading, state‑of‑the‑art 3D camera.

apiCAM offers simultaneous 2D and 3D with a single lens, currently at 30fps (frames per second) and higher in the future. It is already available in commercial products for medical imaging, robotics, Industry4.0 and aims to be in the next generation of XR glasses, tablets, PCs and smartphones.

You will join our Algorithms team, specifically the Digital Verification Group for our state‑of‑the‑art depth and imaging algorithms. This team is part of our R&D; department with experts in physical optics, image processing, algorithms, software and industrial automation.

Responsibilities

Contribute to defining low‑power consumption but extremely efficient digital designs.

Implement testbenches to ensure that the digital designs comply to specifications, are robust and interact correctly with other IP blocks.



Use Xilinx development tools for FPGAs and, in the future, formal verification tools for ASICs.

Collaborate with digital design engineers to redefine and optimise digital IP blocks.

Requirements

Bachelor and/or Master degree in telecommunications, electronics, computer science or related fields.

Experience with HDL‑Hardware Description Languages (Verilog or VHDL) and integration of IP blocks. Development of testbenches using SystemVerilog and UVM methodologies for verification of complex digital designs.

Version control experience with Git or SVN.

Understanding of signal‑processing algorithms in MATLAB, Python and/or C++.

Motivated, willing to work in a team and face big challenges such as the design, verification, and manufacturing of a complex ASIC from the very beginning.

Desirable

Knowledge of basic FPGA architectures and modes of operation.

Experience with state machines.

Design of parametric testbenches and test vectors for complex digital designs.

Finite‑precision modelling in MATLAB or other tools.

We Offer

Competitive salary according to your experience.

Versátil working hours (1–2 teleworking days per week).

Flexible compensation plan (restaurant tickets, transport, childcare, health insurance).

Professional career plan within the company and lifelong learning.

Dynamic start‑up environment.

Fixed contract and professional stability within a demanding but friendly working environment.

We create disruptive technologies, we aim for integral leadership in our disciplines, we enjoy what we do, we live innovation every day, and we invite you to explore the opportunities offered. Come and discover it!

📌 Digital Design Verification Engineer (Paterna) (Madrid)
🏢 Photonic Sensors u0026 Algorithms
📍 Madrid